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| ia82510 data sheet asynchronous serial controller february 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 25 1 - 888 - 824 - 4184 ia82510 asynchronous serial controller data sheet ? ?
ia82510 data sheet asynchronous serial controller february 25, 2011 ia2 11001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 25 1 - 888 - 824 - 4184 copyright 2008 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 87107 intel is a registered trademark of intel corporation miles? is a trademark of innovasic semiconductor, inc. ? ia82510 data sheet asynchronous serial controller february 25, 2011 ia2 11001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 25 1 - 888 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 4 list of tables ................................ ................................ ................................ ................................ ... 5 1. features ................................ ................................ ................................ ................................ ... 6 2. description ................................ ................................ ................................ .............................. 8 3. functional overview ................................ ................................ ................................ ............ 10 3.1 transmitter ................................ ................................ ................................ .................. 10 3.2 receiver ................................ ................................ ................................ ....................... 10 3.3 bus interface ................................ ................................ ................................ ............... 10 3.4 register description ................................ ................................ ................................ .... 11 4. maximum ratings and ac/dc parameters ................................ ................................ .......... 12 5. packaging inf ormation ................................ ................................ ................................ .......... 15 5.1 pdip package ................................ ................................ ................................ .............. 15 5.2 plcc package ................................ ................................ ................................ ............. 16 6. innovasic part number cross - reference ................................ ................................ .............. 17 7. errata ................................ ................................ ................................ ................................ ..... 18 7.1 summary ................................ ................................ ................................ ..................... 18 7.2 detail ................................ ................................ ................................ ........................... 19 8. revision history ................................ ................................ ................................ ................... 24 9. for additional information ................................ ................................ ................................ ... 25 ? ia82510 data sheet asynchronous serial controller february 25, 2011 ia2 11001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 25 1 - 888 - 824 - 4184 list of figures figure 1. package pinout ................................ ................................ ................................ ................ 7 figure 2. functional block diagram ................................ ................................ .............................. 9 figure 3. pdip physical package dimensions ................................ ................................ ............. 15 figure 4. plcc physical package dimensions ................................ ................................ ............ 16 ? ia82510 data sheet asynchronous serial controller february 25, 2011 ia2 11001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 25 1 - 888 - 824 - 4184 list of tables table 1. register summary ................................ ................................ ................................ ........... 11 table 3. absolute maximum ratings ................................ ................................ ........................... 12 table 4. ac parameters ................................ ................................ ................................ ................ 13 table 5. dc parameters ................................ ................................ ................................ ................ 14 table 6. innovasic part number cross - reference for the pdip ................................ .................. 17 table 7. innovasic part number cross - reference for the plcc ................................ ................. 17 table 8. summary of errata ................................ ................................ ................................ .......... 18 table 9. revision history ................................ ................................ ................................ ............. 24 ? ia82510 data sheet asynchronous serial controller february 25, 2011 ia2 11001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 25 1 - 888 - 824 - 4184 1. features form, fit, and function compatible with the intel 82510 p ackaging options available: 28 - pin plastic ( pdip ) or, 28 - lead plastic leaded chip carrier ( plcc ) , leaded or rohs packages available (see figure 1, package pinout) asynchronous serial channel operation separate transmit and receive fifos with programmable threshold programmable baud rate generators up to 288k baud special protocol features C control character recognition C auto echo and loopback modes C 9 - bit protocol support C 5 to 9 bit character format the ia82510 is a "plug - and - play" drop - in replacement for the original ic. innovasic produces replacement ics using its miles ? , or managed ic lifetime extension system, cloning technology. this technology produces replacement ics far more complex than "emulation" while ensuring they are compatible with the original ic. miles ? captures the design of a clone so it can be produce d even as silicon technology advances. miles ? also verifies the clone against the original ic so that even the "undocumented features" are duplicated. this data sheet documents all necessary engineering information about the ia82510 including functional and i/o descriptions, electrical characteristics, and applicable timing. ? ia82510 data sheet asynchronous serial controller february 2 5, 2011 ia211001219 - 05 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 25 1 - 888 - 824 - 4184 figure 1 . package pinout ( 6 ) t x d ( 1 ) d 4 ( 2 ) d 5 ( 3 ) d 6 ( 4 ) d 7 ( 5 ) i n t ( 7 ) v s s ( 8 ) x 2 o r o u t 2 n ( 9 ) x 1 o r c l k ( 1 0 ) s c l k o r r i n ( 1 1 ) d s r n o r t a o r o u t 0 n ( 1 2 ) d c d n o r i c l k o r o u t 1 n ( 1 3 ) r x d ( 1 4 ) c t s n i a 8 2 5 1 0 ( 2 8 ) d 3 ( 2 7 ) d 2 ( 2 6 ) d 1 ( 2 5 ) d 0 ( 2 4 ) a 2 ( 2 3 ) a 1 ( 2 2 ) a 0 ( 2 1 ) v d d ( 2 0 ) r d n ( 1 9 ) w r n ( 1 8 ) c s n ( 1 7 ) r e s e t ( 1 6 ) r t s n ( 1 5 ) d t r n o r t b i a 8 2 5 1 0 ( 6 ) t x d ( 5 ) i n t ( 7 ) v s s ( 8 ) x 2 o r o u t 2 n ( 9 ) x 1 o r c l k ( 1 0 ) s c l k o r r i n ( 1 1 ) d s r n o r t a o r o u t 0 n ( 2 5 ) d 0 ( 2 4 ) a 2 ( 2 3 ) a 1 ( 2 2 ) a 0 ( 2 1 ) v d d ( 2 0 ) r d n ( 1 9 ) w r n ( 4 ) d 7 ( 3 ) d 6 ( 2 ) d 5 ( 1 ) d 4 ( 2 8 ) d 3 ( 2 7 ) d 2 ( 2 6 ) d 1 ( 1 8 ) c s n ( 1 7 ) r e s e t ( 1 6 ) r t s n ( 1 5 ) d t r n o r t b ( 1 4 ) c t s n ( 1 3 ) r x d ( 1 2 ) d c d n o r i c l k o r o u t 1 n 2 8 - p i n p l c c 2 8 - p i n p d i p ? ia82510 data sheet asynchronous serial controller february 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 25 1 - 888 - 824 - 4184 2. description the ia82510 is an asynchronous serial controller that provides a cpu interface to one transmit and one receive cha nnel. it is form, fit, and function compatible with the intel 82510. configuration registers are used to control the serial channel, interrupts, and modes of operation. the cpu controls this device via address and data lines with read/write control. th e cpu also uses this interface to read and write data to receive and transmit data through the serial channel. fifos and various serial modes can be used to help off - load the cpu from transmitting and receiving data. an interrupt line provides an indicat ion to the cpu that the device requires servicing. the device can be configured for 8250a/16450 compatibility. see figure 2, functional block diagram. ? ia82510 data sheet asynchronous serial controller february 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 25 1 - 888 - 824 - 4184 figure 2 . functional block diagram ia82510 bus interface (reset logic, registers, interrupt generation, config., status, rxdata txdata timing (baud rate generators a & b, clocking pin configuration receiver transmitter modem txd rxd x2 or out2n sclk or rin x1 or clk rtsn ctsn dsrn or ta or out0n dcdn or iclk or out1n dtrn or tb a(2:0) d(7:0) rdn wrn csn int reset ? ia82 510 data sheet asynchronous serial controller february 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 25 1 - 888 - 824 - 4184 3. functional overview 3.1 transmitter the t ransmit function consists of a 4 11 bit fifo, and a transmit engine. the 4 11 fifo is configurable as any depth between one and four words inclusive. the transmit engine is responsible for reading the data out of the fifo and placing it in the proper order on the txd pin. the transmit engine is highly configurable to be compatible with numerous formats, including 16450 and 8250 modes of communication. transmit communication parameters that can be programmed include: parity modes stop bits character length fifo depth clocking options rts and cts modes for more details, see section 3.4 , register description . 3.2 receiver the receiver function consists of a 4 11 configurable fifo and a receive engine. the receive engine is responsible for sampling the data on the rxd input pin, formatting the data, and placing the data in the fifo. the receive engine is highly configurable with parameters that include: parity modes stop bits character length fifo depth clocking op tions address matching options control character detection rts and cts modes for more details, see section 3.4, register description . 3.3 bus interface the bus interface is a simple interface that allows a micro - process or or micro - controller to read and write the ia82510 registers. it consists of the following i/o lines: ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 25 1 - 888 - 824 - 4184 a0, a1, a2 : 3 bit address d0 - d7 : 8 bit data rdn: active low read enable wrn: active low write enable csn: active low chip select int: interrupt ou tput reset: chip reset 3.4 register description table 1 presents the register summary. table 1 . register summary register addr bank dlab mode default acr0 111 00 x r/w 00000000 acr1 101 10 x r/w 00000000 bacf 001 11 0 r/w 00000100 bah 001 00 1 r/w 00000000 bal 000 00 1 r/w 00000010 bank 010 x x w 00000000 bbcf 011 11 x r/w 10000100 bbh 001 11 1 r/w 00000000 bbl 000 11 1 r/w 00000101 clcf 000 11 0 r/w 00000000 flr 100 01 x r 00000000 fmd 001 10 x r/w 00000000 ger 001 00 0 r/ w 00000000 gir_bank 010 x x r 00000001 gsr 111 01 x r 00010010 icm 111 01 x w n/a imd 100 10 x r/w 00001100 lcr 011 00 x r/w 00000000 lsr 101 00 x r/w 01100000 mcr 100 100 00 01 x x r/w w 00000000 mie 101 11 x r/w 00001111 msr 110 110 00 01 x x r/ w r 00000000 pmd 100 11 x r/w 11111100 rcm 101 01 x w n/a rie 110 10 x r/w 00011110 rmd 111 10 x r/w 00000000 ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 25 1 - 888 - 824 - 4184 table 2 . register summary (continued) register addr bank dlab mode default rst 101 01 x r 00000000 rxdata 000 0 0 01 0 x r unknown rxf 001 01 x r unknown tcm 110 01 x w n/a tmcr 011 01 x w n/a tmd 011 10 x r/w 00000000 tmie 110 11 x r/w 00000000 tmst 011 01 x r 00110000 txdata 000 00 01 0 x w n/a txf 001 01 x w n/a 4. maximum ratings and ac/dc parameters str esses beyond those listed in table 2 may cause permanent damage to the device. operating the device beyond the conditions indicated in the recommended operating conditions section is not recommended. operation at the absolute maximum ratings may adve rsely affect device reliability. table 3 . absolute maximum ratings parameter rating supply voltage, v dd - 0.3v to +6.0v input voltage, v in - 0.3v to v dd +0.3v input pin current, iin 10 ma, 25 c operating temperature range - 40 c to +85c ambient temperature under bias - 40c to +85c * storage temperature - 55c to +150c lead temperature +300c, 10 sec. power dissipation 155 mw, 125c, 25mhz, 15% toggle * the input and output parametric values are directly related to ambie nt temperature and dc supply voltage. a temperature or supply voltage range other than those specified in the operating conditions above will affect these values and part performance is not guaranteed by innovasic. ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 25 1 - 888 - 824 - 4184 table 4 . ac p arameters parameter min max notes clk period 54 ns 250 ns divide by two clk period 54 ns 108 ns no divide by clk low time 25 ns C C clk high time 25 ns C C clk rise time C 10 ns divide by two measured between 0.3 * vdd and 0.7 * vdd clk fall time C 1 0 ns divide by two measured between 0.3 * vdd and 0.7 * vdd clk rise time C 15 ns no divide by clk fall time C 15 ns no divide by crystal frequency 1 mhz 20 mhz C reset width 8 * clock period C C rts/dtr low setup to reset inactive 6 * clock period C C rts/dtr low hold after reset inactive C clock period C 20 ns C rdn active width 2* clock period +65 ns C C address/csn setup time to rdn active 7 ns C C address/csn hold after rdn inactive 0 ns C C rdn or wrn inactive to active delay clock period +15 ns C C data out float delay after rdn inactive C 40 ns C wrn active width 2 * clock period +15 ns C C address csn setup time to wrn active 7 ns C C address and csn hold time after wrn 0 ns C C data in setup time to wrn inactive 90 ns C C data in hold time after wrn inactive 12 ns C C sclk period 216 ns C 16x clocking mode sclk period 3500 ns C 1x clocking mode rxd setup time to sclk high 250 ns C C rxd hold time after sclk high 250 ns C C txd valid after sclk low C 170 ns C txd delay after rxd C 170 ns remote loopback ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 25 1 - 888 - 824 - 4184 table 5 . dc parameters symbol parameter notes min max unit v il input low voltage (1) - 0.5 0.3 v v ih1 input high voltage - cerdip (1) 2.1 v dd +.3 v v ih2 input high voltage - lcc (2) 2.1 v dd +.3 v v ol out put low voltage (2),(8) 0.4 v v oh output high voltage (3),(8) 2.4 v i li input leakage current (4) 1 a i lo 3 - state leakage current (5) 10 a i cc power supply current (6) 1.12 ma/mhz i pu strapping pullup resistor (12) - 28.3 - 137 a i stby standb y supply current (9) 100 a i ohr rtsn, dtrn strapping current (10) 1.92 ma i olr rtsn, dtrn strapping current (11) n/a ma c in input capacitance (7) 5 pf c io i/o capacitance (7) 6 pf c xtal x1, x2 load 6 pf notes: 1. does not apply to clk/x1 pin, wh en configured as crystal oscillator input (x1). 2. @i ol = 1.92 ma . 3. @i oh = 1.92 ma . 4. 0< v in ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 25 1 - 888 - 824 - 4184 5.2 plcc package figure 4 . plcc physical package dimensions legend: symbol min max a 4.20 4.57 a1 2.29 3.04 d 12.32 12.57 d1 11.43 11.58 d2 9.91 10.92 d3 7.62 bsc e 1.27 bsc e 12.32 12.57 e1 11.43 11.58 e2 9.91 10.92 e3 7.62 bsc note : controlling dimension in millimeters. d 3 e 3 p i n 1 i d e n t i f i e r & z o n e 1 . 2 2 / 1 . 0 7 2 p l c s t o p v i e w d d 1 e e 1 b o t t o m v i e w 0 . 1 0 0 . 5 1 m i n . r 1 . 1 4 / 0 . 6 4 a 1 e 0 . 8 1 / 0 . 6 6 a 0 . 5 3 / 0 . 3 3 d 2 / e 2 s i d e v i e w s e a t i n g p l a n e ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 25 1 - 888 - 824 - 4184 6. innovasic part number cross - reference table 6 . innovasic part number cross - reference for the pdip innovasic part number intel part number package type temperature grades ia82510 - pdw28i - r - 01 lead - free ( rohs - compliant) p82510 tp82510 28 - pin p last ic d ual i n - line p ackage (pdip) (600 mil s) industrial table 7 . innovasic part number cross - reference for the plcc innovasic part number intel part number package type temperature grades ia82510plc28ir 2 lead - free ( rohs - compliant ) n82510 tn82510 28 - lead p lastic l ea ded c hip c arrier (plcc) industrial ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 25 1 - 888 - 824 - 4184 7. errata the following errata are known problems with the ia82510. this is inclusive of all package types and environment grades. a workaround to the identified problem has been provided where possible. all errat a lis ted in production version 00 have been fixed in version 01 of the device unless otherwise noted. version 02 is the result of a migration to a new fab process to ensure long - term supply. it retains the same functionality and errata as the version 01 devic e. 7.1 summary table 8 presents a summary of errata. table 8 . summary of errata errata no. problem ver. 00 ver. 01 ver. 02 1 scrambled data during boot code shuts down uart, however device works for application code. exists fixed fix ed 2 device does not operate at 8 mhz in divide - by - one mode. exists fixed fixed 3 setting clcf to x30, which effectively generates the tx clock from the incoming sclk signal, kills all transmits. exists fixed fixed 4 receiving streamed data has many fra ming errors and corrupt data when connected to some modems. exists fixed fixed 5 transmission of streamed data does not return interrupt. exists fixed fixed 6 receiving streamed data has many framing errors at fast baud rates (divisor=6) through bad mode m lines. exists fixed fixed 7 difficulty starting oscillator with crystal. exists fixed fixed 8 intermittent and temperature sensitive crystal oscillator operation when cycling power. exists fixed fixed 9 auto - acknowledge of interrupts via writing of ls r does not work. exists fixed fixed 10 icm status clear command does not clear lsr/rst overrun error. exists fixed fixed 11 in semi - automatic/ulan mode, the rx fifo is only opened when an address character matches the acr1 or acr0 registers (like full au to mode). exists fixed fixed ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 25 1 - 888 - 824 - 4184 table 7. summary of errata (continued) errata no. problem ver. 00 ver. 01 ver. 02 12 device fails to reset interrupt signal in auto acknowledge mode when character is read from rx fifo. exists fixed fixed 13 rx fifo locks up unexpectedly just after configuration and before starting reception. na exists exists 14 unreliable transmits in auto tx mode. na exists exists 7.2 detail errata no. 1 problem: scrambled data during boot code shuts down uart, ho wever device works for application code. description: the rx fifo is locked, configuration of all registers is done, then the rx fifo is unlocked just before entering loopback mode in both boot and application code before normal operations begin. boot cod e additionally does a blind block read of all registers before normal operations including two reads from the unwritten rx data fifo. rx unlock command is inadvertently incrementing the write pointer. for boot code, the two reads of rx data cause the rea d/write pointers to be permanently out of sync. for application code, the pointers end up synched to the same location, only because the code waits for four characters before reading. this ends up causing an rx overrun, but to our favor because the point ers are now synched. workaround: execute a flush rx fifo command (via rcm register) after configuration and block read is complete. errata no. 2 problem: device does not operate at 8 mhz in divide - by - one mode. description: sy stem testing revealed this operational deficiency. workaround: switch to divide - by - two mode using 2x clock input. ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 25 1 - 888 - 824 - 4184 errata no. 3 problem: setting clcf to x30, which effectively generates the tx clock from the incoming sclk signal, kills all transmits. description: configuration of pmd inadvertently set so ri function is selected instead of sclk function. original intel device allows sclk through anyway, ia82510 suppresses it. workaround: set correct configuration for pmd allows tx clock generation. errata no. 4 problem: receiving streamed data has many framing errors and corrupt data when connected to some modems. description: shortened stop bit followed immediately by next start bit does not correctly detect that start bit. workaround: configure external modem to transmit two stop bits. errata no. 5 problem: transmission of streamed data does not return interrupt. description: stray read of gir sets tx fifo interrupt hold l ogic, but this logic does not reset when ger[1] is de - asserted. workaround: reset logic with write to tx data or avoid stray reads of gir. errata no. 6 problem: receiving streamed data has many framing errors at fast baud rates (divisor=6) through bad modem lines. description: dpll is not robust for rxd signal with more than 1/16 bit time of variation. workaround: none. ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 25 1 - 888 - 824 - 4184 errata no. 7 problem: difficulty starting oscillator with crystal. description: n o internal feedback resistor between x1 and x2. workaround: install external 1 - 10mohm resistor. errata no. 8 problem: intermittent and temperature sensitive crystal oscillator operation when cycling power. description: strappin g state elements apparently transparent latches instead of flip flops. if flip flop powers up to wrong state, crystal oscillator is disabled while reset is active. ok after first reset following power - up. workaround: none. errata no. 9 problem: auto - acknowledge of interrupts via writing of lsr does not work. description: writing lsr directly sets/resets bits 4 through 0. also writing 0 to lsr(0) C rx fifo C clears the rx fifo level as seen by flr. writing zero to any other ls r bits clears the corresponding lsr/rst flag, but also corrupts the fifo location the write pointer is set to, then increments both the write and read pointers. workaround: use other means to service interrupts, such as read of rst or rxd. errata no. 10 problem: icm status clear command does not clear lsr/rst overrun error. description: icm status clear command should clear everything in rst/lsr, msr, and tmst except rst/lsr(0). overrun error was missed. workaround: use other means to service interrupts. ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 25 1 - 888 - 824 - 4184 errata no. 11 problem: in semi - automatic/ulan mode, the rx fifo is only opened when an address character matches the acr1 or acr0 registers (like full auto mode). description: in semi - auto mode, the rx fifo should open on any address character. workaround: none. errata no. 12 problem: device fails to reset interrupt signal in auto acknowledge mode when character is read from rx fifo. description: rd strobe is outside the c s enable, which is outside of the intel datasheet, but apparently still works in the intel device. such a bus cycle allows the read data out, but fails to generate the necessary internal strobe to change pointers. the same problem is found on write acces ses. workaround: force bus interface to bracket rd strobe inside the cs enable. errata no. 13 problem: rx fifo locks up unexpectedly just after configuration and before starting reception. description: an rcm command is execute d with data of xb8. this is an enable rx, flush rx machine, flush rx fifo, and lock rx fifo command done in a single instruction. the flush rx machine should unlock the rx fifo, creating a conflict with the simultaneous lock rx fifo command. the original intel device apparently ignores or gives the lock rx fifo command lower priority in this case. the ia82510 has this priority reversed. apparently, the application software in this case expected the lock rx fifo command to fail. workaro und: do not execute a flush rx fifo and lock rx fifo command simultaneously. break up into separate rcm commands. ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 25 1 - 888 - 824 - 4184 errata no. 14 problem: unreliable transmits in auto tx mode. description: many systems use the rts output to activate the line transceiver. when the transmit mode field in the tmd register is set to semi - auto or automatic mode, rts is controlled by the tx state machine. on the first character, rts asserts at the same time as the start bit on the txd output, whe reas the original intel device asserts rts a full bit time before assertion of the start bit on txd. at full temperature range, the width of the start bit can be altered to the point of confusing the downstream receiver. workaround: change firmware to m anual tx mode to control rts vs. start of character. ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 25 1 - 888 - 824 - 4184 8. revision history table 9 presents the sequence of revisions to document ia211 0 0 1219 . table 9 . revision history date revision description page(s) august 19, 2008 03 corrected co ntrol number and reformatted some elements to meet publication standards. na october 8 , 2008 0 4 corrected part number on cover page, enlarged package pinout and functional block diagram figures, corrected trademark references (p. 2), changed pin to lea d in plcc package pinout figure, changed lead to pin in pdip physical page dimensions figure and part number table, formatted part cross - reference table and errata to meet publication standards, changed part number from ia82510 - plc28i - r - 01 to ia825 10plc28ir2 to reflect current inventory, added for additional information chapter. all february 25, 2011 05 removed packaging options to support the eliminat ion of snpb lead plating options . 17 ? ia82510 data sheet asynchronous serial controller fe bruary 25, 2011 ia211001219 - 0 5 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 25 1 - 888 - 824 - 4184 9. for additional information the ia82510 is a "plug - and - play" drop - in replacement for the original ic. this data sheet documents all necessary engineering information about the ia82510 including functional and i/o descriptions, electrical characteristics, and applicable timing. the innovasic support team is co ntinually planning and creating tools for your use. visit http://www.innovasic.com for up - to - date documentation and software. our goal is to provide timely, complete, accurate, useful, and easy - to - understand infor mation . please feel free to contact our experts at innovasic at any time with suggestions, comments, or questions. innovasic support team 3737 princeton ne suite 130 albuquerque, nm 87107 (505) 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 e - mail: support@innovasic.com website: http://www.innovasic.com ? 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